Microelectronics used for lunar and deep space exploration may be exposed to both extremely low temperatures and various energetic particles in space. Silicon–germanium heterojunction bipolar transistors (SiGe HBTs) are attractive for these space applications due to the superior low-temperature performance and excellent hardness to both total ionizing dose (TID) and displacement damage (DD) without intentional hardening design.^[1–5] However, the main problem of using the unhardened SiGe HBTs in space missions is their susceptibility to single event effect (SEE) due to the existence of the large-area collector–substrate (C–S) junction. When the C–S junction is reversely biased, a great number of the excess carriers deposited by high energy particles with tracks passing through or near the junction will be collected, which can disorder the normal working state of the circuits and lead to serious reliability issues for the system.^[6] Integrated circuits based on SiGe HBTs have been confirmed to suffer low single event upset (SEU) thresholds and large saturated cross sections.^[7–9] Hence, it is crucial to search SEE mitigation techniques for SiGe HBTs aiming at space applications.

Since the SEE results from the collection of excess carriers deposited by incident particles were first identified, there have been in general two kinds of mitigation concepts. The first concept is to reduce the number of excess carriers deposited in the sensitive region. A representative technique is to use SiGe HBTs in the inverse-mode.^[10] This method electrically swaps the emitter for the collector, which isolates the electrical collector (physical emitter) from the lightly doped substrate which is a crucial feature dominating the single event charge collection in bulk SiGe HBTs. However, the problem is that the HBTs are not optimized for inverse-mode so that the performance is significantly degraded.^[11] The second concept is to reduce the number of carriers that transport to the collecting node. This path was previously implemented by introducing an additional reverse biased p–n junction formed between the p-substrate and an n⁺ guard ring, thus resulting in a secondary electric field.^[12] As a result, part of the carriers that are going to be collected by the collector will be collected by the n⁺ guarding ring. The added n⁺ guard ring is also called dummy collector in ^[13]. This technique is effective in reducing charges outside the deep trench isolation (DTI) where the charge collection is dominated by diffusion and it may also lead to area penalty. However, most of the existing mitigation techniques are based on SiGe HBTs fabricated with DTI, while few results concerning the non-DTI SiGe HBTs are available. Although SiGe HBT without DTI has a larger sensitive area than DTI SiGe HBT, its charge collection when the ion penetrates the active region is much smaller than DTI SiGe HBT’s, which can lead to a higher SEU threshold.^[14]

In this work, we evaluate the effectiveness of two SEE mitigation techniques in domestic non-DTI SiGe HBT based on technology computer aided design (TCAD) simulation. The first is the back junction technique, which was originally presented by Niu et al. in DTI SiGe HBT.^[15] The basic idea of this technique is to add an n⁺ layer several micrometers beneath the subcollector to form a back junction between the substrate and n⁺ layer. On the one hand, this layer cut off the ion track so that the total quantity of charges that can be collected is limited by the thickness of the substrate above it. On the other hand, the deposited charges will be collected by both the C–S junction and the added back junction. In ^[15] that authors mainly considered the condition when the ions strike at the center of the device, where the charge collection is dominated by field-funnelling effect. However, it is also necessary to consider the influence of the back junction on event far from C–S junction in non-DTI SiGe HBT. This event can also result in significant charge collection through diffusion, thus making the sensitive area much larger than the area of the C–S junction.^[16] The second technique is to form a p⁺ buffer layer around the collector through ion implantation. This p⁺ layer provides a region with a high rate of recombination with the excess electrons which are responsible for the charge collection on collector, thus the charge collection on collector will be reduced. Simply increasing the doping level of the entire substrate may also result in reducing charge collection, but this will significantly reduce the substrate resistance and lead to other problems such as substrate coupling in mixed-signal circuits. However, the use of a buffer layer with a thickness of several micrometers can avoid this problem.

Based on three-dimensional (3D) TCAD simulation, a quantitative comparison of heavy ion-induced charge collection is performed between the hardened SiGe HBT and the conventional SiGe HBT. The influence of possible factors are also investigated and the mechanisms are discussed. In addition, the mitigation results by the two techniques are also compared to find their advantages.

The device investigated is a domestic vertical N–P–N SiGe HBT. The top-down and cross section views of the conventional device obtained by TCAD are shown in Fig. 1(a). The active emitter area is . The intrinsic base region is formed by epitaxially growing the SiGe layer, the content of Ge changes gradually from 0% at the emitter–base junction and the base–collector junction to 20% in the intrinsic base, forming two graded heterojunctions. The thickness of the base is . The epitaxial base region is located above the local oxidation of silicon (LOCOS). The C–S junction area is . The substrate contact is extracted through a heavily doped ring wall at the edge of the device. More information about the device can be found in ^[17] and ^[18]. The TCAD model is calibrated with the parameters measured by using Keithley 4200 and the heavy-ion-induced SEE results.^[19–22] The structure of back junction SiGe HBT is shown in Fig. 1(b). An n⁺ buried layer below the collector divides the lightly doped substrate into two parts. The part below the n⁺ layer has no electrical connects with the substrate, so we call this part the supporting substrate. The part above the n⁺ layer is connected to the substrate electrode and this part is the real substrate. In the following parts, the word “substrate” refers to the upper part unless otherwise stated. The contact to n⁺ layer is lead out by the n⁺ plugs. The thickness of the substrate is denoted as L_s, the thickness of the n⁺ layer is denoted as L_n, the doping concentration of the n⁺ layer and n⁺ plugs is denoted as D_n, the number of n⁺ plugs is denoted as N. The structure of the SiGe HBT with a p⁺ buffer layer is shown in Fig. 1(c). A p⁺ layer with Gaussian doping distribution is formed around the collector. The peak value of the Gaussian profile is denoted as D_p and the depth is denoted as L_p. According to the layouts, no additional area penalty is introduced by the two mitigation techniques.

Fig. 1.

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	Fig. 1. Top down and cross-section view of (a) conventional HBT, (b) back junction HBT, and (c) buffer layer HBT.

In the SEE simulation, a linear charge deposition (LCD) of 0.4 pC/ , which is equivalent to a linear energy transfer (LET) of is selected. This LET value is between the LET of 230-MeV Ge ( and 240-MeV Br ( . These two ion types are often used in accelerator heavy ion SEE experiments. The ion track is generated by using Gaussian waveform in which the 1/e characteristic time scale is 2 ps, the peak of the Gaussian distribution occurs at 5 ps, and the 1/e characteristic radius is . All the ions are at normal incidence. The devices are in the “off state”, the emitter, base, and collector are biased with 0 V, while the substrate is biased with −3 V. This is shown to be the most sensitive state to SEE in SiGe circuit. In the back junction structure, the n⁺ plug is also connected to 0 V to keep the voltage of the n⁺ layer at the same level as the voltage of the collector. To better evaluate the effectiveness of the two mitigation techniques, the influences of some structure details are considered. For the back junction structure, the influences of L_s, L_n, D_n, and N are investigated; while for the p⁺ buffer layer structure, the influences of D_p and L_p are investigated.

Figure 15 shows a comparison between the mitigation results obtained by using the two techniques. For the back junction structure, , , and N = 8. For the buffer layer structure, and . The results from the two techniques have something in common. In the conventional device, the area enclosed by the p⁺ ring wall is found to be sensitive to SET, while for the devices using the mitigation techniques, the charge collection outside the C–S junction is significantly reduced and the sensitive area is confined by the boundary of C–S junction. In addition, the charge collection of events inside the C–S junction is also reduced to a large extent. For the given parameters, the device with back junction structure shows better mitigation results than that with buffer layer structure. However, to obtain good mitigation results, the back junction structure significantly reduces the substrate thickness so that the maximum working voltage should be lower than that in the conventional and buffer layer structure to avoid punch through. In addition, the formation of the n⁺ plugs and the metal contacts to them need additional masks. The added contacts to n⁺ plugs will also make the metallization in highly integrated digital circuits more complicated. While for the buffer layer structure, no alteration in the device geometry is required. Only the formation of the buffer layer needs additional masks.

Fig. 15.

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	Fig. 15. Plots of collector charge collection as a function of ion strike position for SiGe HBT with different structures.

Finally, neither of the two techniques with the parameters given above affect the AC and DC characteristics of the device, as evidenced by the Gummel characteristic and cutoff frequency (f_T) behavior shown in Fig. 16.

Fig. 16.

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	Fig. 16. Influence of mitigation techniques on (a) Gummel characteristics and (b) fT.

In this work, we investigate two mitigation techniques for reducing collector charge collection in non-DTI bulk SiGe HBT by using back junction and p⁺ buffer layer. After properly adjusting the structure parameters, the two techniques can significantly reduce the charge collection induced by events inside and outside the C–S junction without affecting the DC or AC characteristics. In addition, they more effectively reduce the charge collections of events outside the C–S junction, thus leading to a significant decrease of the sensitive area to SEE. For the back junction structure, reducing the substrate while increasing thickness and doping level of the n⁺ layer as well as n⁺ plug number will help to obtain better mitigation results. For the buffer layer structure, the improvement of effectiveness is based on higher peak concentration and higher depth of the layer.

The authors would like to thank the Institute of Microelectronics, Tsinghua University, for providing the prototype device.